Impedance and duty cycle calibration in a driver circuit and a receiver circuit
US9385712B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Jul 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some of the embodiments of the present disclosure provide a method including: communicating, by a first pin of an integrated circuit, with a device over a communication link, wherein the first pin is associated with a first impedance; selecting a plurality of impedance values for the first impedance; for ones of the plurality of impedance values, (i) transmitting a corresponding digital signal from the first pin over the communication link and (ii) generating a corresponding signal eye opening for the corresponding digital signal, such that a plurality of signal eye openings corresponding to a plurality of digitals signals for the corresponding plurality of impedance values are generated; comparing the plurality of signal eye openings; selecting a first impedance value of the plurality of impedance values; and transmitting signals over the communication link, with the first impedance being tuned to the first impedance value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.