Multi-threshold flash NCL logic circuitry with flash reset
US9385715B2 · kind B2 · utility
4Cited by
41References
17Claims
0Family size
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Inventor
Key dates
| Filing date | May 4, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | May 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/58
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Multi-threshold flash Null Convention Logic (NCL) includes one or more high threshold voltage transistors within a flash NCL gate to reduce power consumption due to current leakage by transistors of the NCL gate. High-threshold voltage transistors may be added and/or may be used in place of one or more lower voltage threshold transistors of the NCL gate. A high-Vt device is included in the pull-up path to reduce power when the flash NCL logic gate is in the null state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.