Adaptive correction of interleaving errors in time-interleaved analog-to-digital converters
US9385737B1 · kind B1 · utility
3Cited by
14References
23Claims
0Family size
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Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Apr 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system includes an interleaved analog-to-digital converter (ADC) comprising a plurality of sub-ADCs, where each of the plurality of sub-ADCs has an adjustable timing. The system includes a data analyzer that analyzes an output of the interleaved ADC, that estimates timing mismatches of the plurality of sub-ADCs, and that corrects the timing mismatches by adjusting the adjustable timing of one or more of the plurality of sub-ADCs based on the estimated timing mismatches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.