Sigma-delta ADC with dither
US9385745B1 · kind B1 · utility
3Cited by
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20Claims
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Key dates
| Filing date | Sep 1, 2015 |
| Grant date | Jul 5, 2016 |
| Priority date | — |
| Expiry date | Sep 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reducing spurious noise tones in sigma-delta analog-to-digital converters (ADCs) are described. A dither signal may be added to two differential input signals of a pseudo-differential sigma-delta ADC. The dither signal may be generated by a pseudo-random bit sequence generator and applied to two input buffers, which add the dither signal to received differential analog input signals. The dithered signals may be digitized by two independent sigma-delta ADCs and then subtracted to remove the dither signal from an overall digital output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.