Reducing read-after-write errors in a non-volatile memory system using an old data copy
US9389792B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2015 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Dec 7, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Following a relocation write in which data is relocated without update from an old physical location to a new physical location within the non-volatile memory array, a controller defers an update of a logical-to-physical translation (LPT) entry to associate a logical address of the data with a new physical address of the new physical location, for example, for a time-out period. During deferment of the update to the LPT entry, the controller services a read request targeting the logical address from data at the old physical location. In response to no update to the data being made during deferment of the update to the LPT entry, the controller performs the deferred update to the LPT entry. In response to an update to the data being made during the deferment of the update to the LPT entry, the controller refrains from performing the deferred update to the LPT entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.