Device and method for implementing address buffer management of processor
US9389859B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2011 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Oct 30, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3552
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a device for implementing address buffer management of a processor, including: an assembler configured to perform operations to obtain intermediate values when the assembler encodes a set instruction for an address automatic-increment value and boundary values, and to encapsulate the intermediate values into the set instruction for the address automatic-increment value and boundary values; and a processor configured to determine, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation, so as to achieve the address buffer management. The disclosure also provides a method for implementing address buffer management of a processor, including: a processor decodes a set instruction for an address automatic-increment value and boundary values to obtain intermediate values, and determines, according to the intermediate values, whether to perform the address automatic-increment operation or the address automatic-decrement operation when the processor performs a load or store instruction, so as to realize the address buffer management. Through the device and the method of the discl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.