Debug system, and related integrated circuit and method
US9389979B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 26, 2013 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | May 21, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.