Logic absorption techniques for programmable logic devices
US9390210B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 2014 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Oct 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/347
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.