Methods of preparing layouts for semiconductor devices, photomasks formed using the layouts, and semiconductor devices fabricated using the photomasks
US9390214B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Dec 19, 2014 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Dec 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.