Device and method for image scaling
US9390471B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2015 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Aug 19, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T3/4007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An image processing circuit includes a scaling processing section having interpolation coefficient inputs, an interpolation coefficient rearrangement section and an interpolation coefficient feeding section. The interpolation coefficient feeding section feeds first interpolation coefficients to the interpolation coefficient rearrangement section. The interpolation coefficient rearrangement section is configured to feed interpolation coefficients selected from the first interpolation coefficients and second interpolation coefficients obtained by subtracting the first interpolation coefficients from a predetermined value, respectively, to the respective interpolation coefficient inputs of the scaling processing section in response to coordinates of a target pixel of the output image. The scaling processing section is configured to generate pixel data of the target pixel of the output image by performing interpolation on the pixel data of pixels of the input image, using the interpolation coefficients fed to the interpolation coefficient inputs from the interpolation coefficient rearrangement section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.