Patent · US Active

Dynamic subroutine linkage optimizing shader performance

US9390542B2 · kind B2 · utility

0Cited by

5References

20Claims

0Family size

Assignee

MICROSOFT TECHNOLOGY LICENSING, LLC · US

Inventors

Michael V. Oneppo · Seattle, US
Craig Peeper · Kirkland, US
Andrew L. Bliss · Bellevue, US
John Lee Rapp · Seattle, US
Mark M. Lacey · Seattle, US

Key dates

Filing date	Nov 11, 2013
Grant date	Jul 12, 2016
Priority date	—
Expiry date	Dec 19, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG06T2200/28
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.