Patent · US Active

SRAM with via displacement

US9390765B2 · kind B2 · utility

1Cited by

1References

14Claims

0Family size

Assignee

Synaptics Display Devices GK · JP

Inventors

Kazuhiko Sato · Mito, JP
Yasuhiro Fujii · Tokyo, JP

Key dates

Filing date	Jun 11, 2013
Grant date	Jul 12, 2016
Priority date	—
Expiry date	Mar 14, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The SRAM memory cell includes a metal wiring line having a titanium or tantalum film in a bottom layer, and a via having a tungsten plug. The via is arranged on the metal line following a layout rule which permits the misalignment. In arranging the upper-layer via with a tungsten plug on the metal line, one side of the via is disposed to be adjacent to one end of the metal line with a margin smaller than an alignment accuracy, and the lower-layer via is laid out far away from the end of the metal line as possible. The reduction in the yield, caused by the problem of the contact with the lower-layer via being broken or increased in resistance at occurrence of misalignment, can be suppressed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.