Patent · US Active

Configurable delay circuit and method of clock buffering

US9390788B2 · kind B2 · utility

0Cited by

1References

14Claims

0Family size

Assignee

NVIDIA Corporation · US

Inventors

Hwong-Kwo Lin · Palo Alto, US
Lei Wang · Singapore, SG
Spencer Gold · Pepperell, US
Zhenye Jiang · Santa Clara, US

Key dates

Filing date	Jul 27, 2015
Grant date	Jul 12, 2016
Priority date	—
Expiry date	Jul 27, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/4076
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An SRAM clock circuit and an SRAM. In one embodiment, the SRAM clock circuit includes: (1) a plurality of transistor stacks optionally serially electrically couplable to form a configurable delay path through which a clock signal is buffered, and (2) a delay path select circuit respectively electrically coupled between pairs of the plurality of transistor stacks and operable to selectively electrically couple the plurality of transistor stacks to a base delay path, thereby activating the configurable delay path based on a desired delay.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.