Semiconductor device
US9391064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to provide a semiconductor device having high ESD tolerance, a semiconductor device (IC) is formed so that: a ground voltage wiring (22a) is electrically connected at one end in a wiring direction thereof to a wiring (22b) extending from a ground voltage pad used for external connection; an input voltage wiring (23a) is electrically connected at one end in a wiring direction thereof to a wiring (23b) extending from an input voltage pad used for external connection; and the one end of the ground voltage wiring (22a) and the one end of the input voltage wiring (23a) are substantially opposed to each other across a center of an NMOS transistor (10).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.