Configurable multiply-accumulate
US9391621B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2013 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Mar 23, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Field programmable gate arrays (FPGA) contain, in addition to random logic, also other components, such as processing units, multiply-accumulate (MAC) units, analog circuits, and other elements, configurable with respect of the random logic, to enhance the capabilities of the FPGA. A circuit for a filed configurable MAC unit is provided to allow various configurations of ADD, SUBTRACT, MULTIPLY and SHIFT functions. Optionally, registered input and registered output support a multi-cycle path. A configuration of a constant facilitates the configuration of the circuit to perform infinite impulse response (IIR) and finite impulse response (FIR) functions in hardware.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.