Decoder and decoding method thereof for min-sum algorithm low density parity-check code
US9391647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2014 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure illustrates a decoder for min-sum algorithm low density parity-check code. The decoder is adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes a plurality of calculation units, and the memory includes a plurality of memory units. Each calculation unit includes a check node unit, a first message re-constructor and a second message re-constructor. The calculation module divides the coding data into several data groups, and the data group is calculated by each calculation unit. The check node unit generates a stored-form of a calculating result by calculating the respective data group. The calculating result is reconstructed by the first message re-constructor and summed with the following data group. The memory unit stores the respective calculating result generated from the calculation unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.