Processor noise mitigation using differential crictical path monitoring
US9395782B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Jan 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach for power supply noise mitigation on a processor is provided. In one aspect, the approach comprises a central computing unit operatively coupled to the processor to execute program operations. The approach further comprises a calibration circuit adapted to determine a first threshold on the processor to be used for comparison performed dynamically through the use of a detection circuit. A detection circuit adapted to dynamically monitor system operation of the processor and indicate if the first threshold is violated and a counting circuit adapted to prevent voltage from drooping if one or more voltage sensing measurements violates the first threshold are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.