Conditional memory fault assist suppression
US9396056B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Mar 25, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/073
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode stage to decode one or more instruction specifying: a set of memory operations, one or more register, and one or more memory address. One or more execution units, responsive to the one or more decoded instruction, generate said one or more memory address for the set of memory operations. Instruction execution logic records one or more fault suppress bits to indicate whether one or more portion of the set of memory operations are masked. Fault generation logic is suppressed from considering a memory fault corresponding to a faulting one of the set of memory operations when said faulting one of the set of memory operations corresponds to a portion of the set of memory operations that is indicated as masked by said one or more fault suppress bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.