Memory system including nonvolatile memory devices which contain multiple page buffers and control logic therein that support varying read voltage level test operations
US9396796B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Nov 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.