Enhanced flash chip and method for packaging chip
US9396798B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2013 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Jun 24, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1438
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An enhanced Flash chip and a method for packaging chip, wherein the enhanced Flash chip comprising: a FLASH and a RPMC, packaged integrally; the FLASH and the RPMC each comprising: a first internal IO pin and a second internal IO pin; the FLASH and the RPMC being further provided with a jumper window, one end of which is mutually connected to the first internal IO pin of the FLASH or the RPMC and the other end of which is mutually connected to the first internal IO pin of the RPMC or the FLASH; the second internal IO pin of the FLASH and the second internal IO pin of the RPMC being mutually connected. The enhanced Flash chip provided in the present application may effectively reduce design complexity and chip manufacturing cost, avoid the crossing of the metal lead wires in the chip package, and increase the yield of chip packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.