Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patterns
US9396988B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2015 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | May 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes sequentially forming an interlayer insulating layer and a hard mask pattern including a first opening on a substrate including a lower pattern, forming a trench exposing the lower pattern in the interlayer insulating layer using the hard mask pattern, forming a liner layer including a first part formed along sidewalls and a bottom surface of the trench and a second part formed along a top surface of the hard mask pattern, forming a sacrificial pattern exposing the second part of the liner layer in the trench, removing the second part of the liner layer and the hard mask pattern using the sacrificial pattern, and after the removing of the hard mask pattern, removing the sacrificial pattern to expose the first part of the liner layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.