Semiconductor device
US9397088B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/60
Abstract
In order to provide a semiconductor device having high ESD tolerance, a plurality of source wirings (22) are formed of metal films having the same shape and electrically connect a plurality of sources (12) to a ground voltage wiring (22a), respectively, a plurality of drain wirings (23) are formed of metal films having the same shape and electrically connect a plurality of drains (12) to an input voltage wiring (23a), respectively, and a plurality of gate wirings (21) are formed of metal films having the same shape and electrically connect a plurality of gates (11) to the ground voltage wiring (22a), respectively. Further, a back gate wiring (24) is formed of a metal film and electrically connects a back gate (14) to the ground voltage wiring (22a), and the back gate wiring (24) is separated from the source wiring (22) formed on the source (12).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.