Dual path double zero continuous time linear equalizer
US9397623B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2015 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Feb 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45494
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transadmittance amplifier stage is coupled to a transimpedance amplifier stage to form a continuous time linear equalizer. The transadmittance amplifier stage has first and second gain paths and is configured to input a first signal and output a second signal. The first gain path is configured to provide a DC gain recovery and a first high frequency gain to the first signal. The second gain path is configured to provide a second high frequency gain to the first signal. The second signal is generated by the transadmittance amplifier stage based on the gain recovery of the first signal and the high frequency gains of the first signal. The transimpedance amplifier stage is configured to input the second signal from the transadmittance amplifier stage and convert the second signal to an output voltage signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.