Delay circuit
US9397646B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Dec 13, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for delay control are described herein. In one embodiment, a delay circuit comprises a first delay path and a second delay path. The delay circuit also comprises a plurality of switches, wherein each switch is coupled between different points on the first and second delay paths, and each switch is configured to turn on or off in response to a respective one of a plurality of select signals. The delay circuit further comprises a multiplexer having a first input coupled to an output of the first delay path, a second input coupled to an output of the second delay path, and an output coupled to an output of the delay circuit, wherein the multiplexer is configured to selectively couple one of the outputs of the first and second delay paths to the output of the delay circuit in response to a second select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.