Shared divide by N clock divider

US9397667B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS DEUTSCHLAND GMBH · DE

Inventor

• Arni Ingimundarson · Munich, DE

Key dates

• Filing date: Sep 4, 2014
• Grant date: Jul 19, 2016
• Expiry date: Sep 4, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K23/68
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals.