Methods and circuits for reducing clock jitter
US9397823B2 · kind B2 · utility
4Cited by
4References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | Oct 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.