Packet scheduling in a network processor
US9397938B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 28, 2014 |
| Grant date | Jul 19, 2016 |
| Priority date | — |
| Expiry date | May 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE models the packet through a model of the network topology, determining an order in which to transmit the packet among a number of packets based on the modeling. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.