Patent · US Active

High speed FPGA boot-up through concurrent multi-frame configuration scheme

US9401190B1 · kind B1 · utility

5Cited by

2References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Jun Tan · Kepong, MY
Kiun Kiet Jong · Merang, MY
Lai Pheng Tan · Bukit Mertajam, MY

Key dates

Filing date	Apr 13, 2015
Grant date	Jul 26, 2016
Priority date	—
Expiry date	Apr 13, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/1776
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.