Semiconductor device and fabrication method thereof
US9401426B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 11, 2014 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Dec 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/40
Abstract
A semiconductor device includes a gate stack, an isolation structure and a strained feature. The gate stack is over a substrate. The isolation structure is in the substrate. The strained feature is disposed between the gate stack and the isolation structure and disposed in the substrate. The strained feature includes an upper surface adjacent to the isolation structure having a first crystal plane and a sidewall surface adjacent to the gate stack having a second crystal plane. The first crystal plane is different from the second crystal plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.