Synchronization method, and corresponding device and integrated circuit
US9401799B2 · kind B2 · utility
1Cited by
4References
16Claims
0Family size
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Key dates
| Filing date | Mar 18, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Mar 18, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0045
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The operation of a circuit exhibiting a delay that is subject to a time spread as a function of process, voltage, and temperature variations is synchronized with a synchronization signal. A digital delay corresponding to the time spread is applied to the synchronization signal. The digital delay is generated via cascaded delay elements having respective delay values and by controlling the number of cascaded delay elements in the circuit that are applied to the synchronization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.