Clock data recovery system for Serdes
US9401800B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 14, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Sep 13, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/4382
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A clock data recovery system is provided. A CTLE generates a first equalized signal. An adder superposes the first equalized signal and a feedback equalization signal and generates a superposed signal. A first error slicer slices the superposed signal according to a clock signal and a reference voltage and generates a first error signal. A second error slicer slices the superposed signal according to the clock signal and a second slicing voltage. A data slicer slices the superposed signal according to the clock signal and a third slicing voltage and generates a data signal. A CDR circuit generates the clock signal. An adaptive filter receives the data signal and the first error signal, and generates the reference voltage and a DFE coefficient set. A DFE receives the data signal and the DFE coefficient set, and generates the feedback equalization signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.