Apparatus and method for channel estimation
US9401825B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2015 |
| Grant date | Jul 26, 2016 |
| Priority date | — |
| Expiry date | Dec 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2647
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A channel estimation apparatus includes a de-map circuit to map multiple preambles corresponding to multiple channels into real part (I) and imaginary part (Q) in QPSK coordinate. The costas channel estimation circuit receives the real part (I) and the imaginary part (Q) to operate corresponding to one of the BPSK structure and the QPSK structure to proceed calculation of (Q−I)*Sign (I+Q) or Q*Sign (I)−I*Sign (Q) for outputting an output value, wherein Sign(x) represents a sign circuit taking a sign of the x value. The loop filter circuit filters the output value under time domain. The smooth circuit receives the output of the loop filter circuit to perform smooth processing under frequency domain and then feeds back the same to the de-map circuit to continue channel estimation of a next loop, wherein the phases of the preambles are adjusted according to a direction of the output value approaching to zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.