Patent · US Active

Apparatus and method to implement power management of a processor

US9405340B2 · kind B2 · utility

1Cited by

2References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Baskaran Ganesan · Bengaluru, IN
Eric J. Dehaemer · Shrewsbury, US
Vinod Ambrose · Marlborough, US
Harjinder Hullon · Santa Clara, US
Joseph R. Doucette · Waltham, US
Seow Fung Ooi · Air Itam, MY
Min Huang · Shanghai, CN
Zhiguo Wang · Dachau, DE
Yin-Lung Lu · Hillsboro, US
William J. Bowhill · Marlboro, US

Key dates

Filing date	Jun 27, 2013
Grant date	Aug 2, 2016
Priority date	—
Expiry date	May 17, 2034

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating voltage of each core at each of a plurality of frequencies. Each cluster includes a unique set of cores and at least one cluster includes at least two of the cores. The processor also includes a power control unit (PCU) including frequency/voltage control logic, responsive to a frequency change request for a first core of a first cluster, to determine an operating voltage for the first core from a first cluster voltage-frequency (V-F) table associated with the first cluster. The first cluster V-F table uniquely specifies a corresponding operating voltage at each of a plurality of frequencies of operation of the cores of the first cluster. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.