S12 TX FIR architecture
US9405511B2 · kind B2 · utility
0Cited by
1References
25Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Oct 27, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Feb 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A FIR transmit architecture uses multiple driver divisions to allow signals with different delays to be summed into the output signal by the driver itself. The architecture includes a first multiplexer, a plurality of delay cells, a plurality of sign blocks, a switch block, a second multiplexer, and a plurality of drivers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.