Method and apparatus for injecting errors into memory
US9405646B2 · kind B2 · utility
3Cited by
5References
20Claims
0Family size
Inventors
Key dates
| Filing date | Sep 29, 2011 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Feb 15, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3698
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.