Processor and memory control method for allocating instructions to a cache and a scratch pad memory
US9405683B2 · kind B2 · utility
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21Claims
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Key dates
| Filing date | Mar 11, 2011 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Nov 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and a memory management method are provided. The processor includes a processor core, a cache which transceives data to/from the processor core via a single port, and stores the data accessed by the processor core, and a Scratch Pad Memory (SPM) which transceives the data to/from the processor core via at least one of a plurality of multi ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.