Image processing techniques for tile-based rasterization
US9406100B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Nov 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with vertex shading and binning triangles. The techniques can also provide better load balancing among a set of cores, and hence provide better performance. A bounding volume is generated to represent a geometry group. Culling takes place to determine whether a geometry group is to have triangles rendered. Vertex shading and association of triangles with tiles can be performed across multiple cores in parallel. Processing resources are allocated for rasterizing tiles whose triangles have been vertex shaded and binned over tiles whose triangles have yet to be vertex shaded and binned. Rasterization of triangles of different tiles can be performed by multiple cores in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.