Graphics processing systems

US9406155B2 · kind B2 · utility

Assignee

• Arm Limited · GB

Inventors

• Jon Erik Oterhals · Trondheim, NO
• Daren Croxford · Cambridge, GB
• Lars Ericsson · Cambridge, GB
• Jørn Nystad · Trondheim, NO
• Eivind Liland · Trondheim, NO

Key dates

• Filing date: Sep 24, 2010
• Grant date: Aug 2, 2016
• Expiry date: May 18, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G09G2320/103
• WIPO field: Audio-visual technology
• WIPO sector: Electrical engineering

Abstract

A graphics processor 1 includes after its tile rendering logic 40, a transaction elimination unit 5 that includes data block generation logic 41 and block comparison logic 43. The block generation logic 41 generates data blocks from the rendered tiles produced by the tile rendering logic 40. The data blocks are then stored in buffers 42. Comparison logic 43 then compares a new data block with the previous data block (which will already be stored in the buffers 42), and generates an output metadata bit indicating whether the blocks can be considered to be the same or not, on the basis of the comparison. The meta-data output bits are stored appropriately in a meta-data bitmap 45 in main memory 2 that is associated with the output data array in question. If the blocks are determined to be different by the comparison logic then the new data block is written from the buffers 42 to the frame buffer 44 in the main memory 2. On the other hand, if the two blocks are considered to be similar to each other, the new block is not written into the data array in the frame buffer 44.