Memory with local-/global bit line architecture and additional capacitance for global bit line discharge in reading
US9406351B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Apr 1, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a memory unit comprising one or more global bit lines connected to a sense amplifier, and a plurality of memory cells that are grouped into a plurality of memory cell groups, each memory cell group having one or more local bit lines operatively connected to each of the memory cells in the memory cell group. Each memory cell group is configured such that, when a memory cell of the memory cell group is being read, the one or more local bit lines of the memory cell group are provided as inputs to a logic circuit and are not connected to the global bit lines, the logic circuit being configured to cause a capacitance element to be connected to one of the one or more global bit lines in dependence upon the states of the one or more local bit lines of the memory cell group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.