Circuit and method for improving ESD tolerance and switching speed
US9406695B2 · kind B2 · utility
11Cited by
260References
17Claims
0Family size
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Key dates
| Filing date | Oct 22, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Oct 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/713
Abstract
Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.