Vertically stacked image sensor
US9406713B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Oct 17, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A vertically stacked image sensor having a photodiode chip and a transistor array chip. The photodiode chip includes at least one photodiode and a transfer gate extends vertically from a top surface of the photodiode chip. The image sensor further includes a transistor array chip stacked on top of the photodiode chip. The transistor array chip includes the control circuitry and storage nodes. The image sensor further includes a logic chip vertically stacked on the transistor array chip. The transfer gate communicates data from the at least one photodiode to the transistor array chip and the logic chip selectively activates the vertical transfer gate, the reset gate, the source follower gate, and the row select gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.