Methods for fabricating self-aligning semiconductor hetereostructures using nanowires
US9406823B2 · kind B2 · utility
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11Claims
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Key dates
| Filing date | Jul 11, 2014 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Jul 11, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/762
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.