Low noise, programmable gain current buffer
US9407296B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2016 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Feb 15, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/18
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off, during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.