System and method using cascaded single partity check coding
US9407398B2 · kind B2 · utility
13Cited by
16References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 8, 2013 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Feb 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0063
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method including a parity bit encoder for encoding each n−3 bits of data to be transmitted with three parity check bits to produce blocks of n bits (n−3 information bits plus three parity bits associated with the n information bits). Each of the blocks of n bits are Gray mapped to three QAM symbols that are modulated onto an optical wavelength and transmitted to a receiver. A maximum a posteriori (MAP) decoder is used at the receiver to correct for cycle slip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.