Patent · US Active

System and method for statistical post-silicon validation

US9411007B2 · kind B2 · utility

1Cited by

5References

20Claims

0Family size

Assignee

THE REGENTS OF THE UNIVERSITY OF MICHIGAN · US

Inventors

Valeria Bertacco · Ann Arbor, US
Andrew DeOrio · Ann Arbor, US
Daya Shanker Khudia · Ann Arbor, US

Key dates

Filing date	Oct 29, 2012
Grant date	Aug 9, 2016
Priority date	—
Expiry date	Mar 18, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/263
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

The system and method described herein relate to a bug positioning system for post-silicon validation of a prototype integrated circuit using statistical analysis. Specifically, the bug positioning system samples output and intermediate signals from a prototype chip to generate signatures. Signatures are grouped into passing and failing groups, modeled, and compared to identify patterns of acceptable behavior and unacceptable behavior and locate bugs in space and time.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.