Synchronization in a computing device
US9411363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Dec 10, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides an apparatus. The apparatus includes a processor, a chipset, a memory to store a process, and logic. The processor includes one or more core(s) and is to execute the process. The logic is to acquire performance monitoring data in response to a platform processor utilization parameter (PUP) greater than a detection utilization threshold (UT), identify a spin loop based, at least in part, on at least one of a detected hot function and/or a detected hot loop, modify the identified spin loop using binary translation to create a modified process portion, and implement redirection from the identified spin loop to the modified process portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.