Coprocessor dynamic power gating for on-die leakage reduction
US9411404B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2014 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Nov 6, 2034 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus is disclosed for managing operational modes of a processor. The apparatus may include the processor which may include a coprocessor, an instruction queue, and a monitoring circuit for detecting instructions for the coprocessor in the instruction queue. The monitoring circuit may detect when the instruction queue holds no instructions for the coprocessor. If the instruction queue holds no instructions for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor consumes less power. The monitoring circuit may detect an instruction for the coprocessor in the instruction queue. In response to the instruction for the coprocessor, the coprocessor may be placed into a mode in which the coprocessor may execute the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.