Processors, methods, systems, and instructions to consolidate unmasked elements of operation masks
US9411593B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Oct 11, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction processing apparatus of an aspect includes a plurality of operation mask registers. The apparatus also includes a decode unit to receive an operation mask consolidation instruction. The operation mask consolidation instruction is to indicate a source operation mask register, of the plurality of operation mask registers, and a destination storage location. The source operation mask register is to include a source operation mask that is to include a plurality of masked elements that are to be disposed within a plurality of unmasked elements. An execution unit is coupled with the decode unit. The execution unit, in response to the operation mask consolidation instruction, is to store a consolidated operation mask in the destination storage location. The consolidated operation mask is to include the unmasked elements from the source operation mask consolidated together. Other apparatus, methods, systems, and instructions are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.