Load balance connections per server in multi-core/multi-blade system
US9411656B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2009 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | Apr 8, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.