Error correction in memory
US9411683B2 · kind B2 · utility
8Cited by
1References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 26, 2013 |
| Grant date | Aug 9, 2016 |
| Priority date | — |
| Expiry date | May 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3715
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Apparatus, systems, and methods for error correction in memory are described. In one embodiment, a memory controller comprises logic to load an error correction codeword retrieved from a memory and apply a first error correction decoder to decode the error correction codeword, wherein the first error correction decoder implements a bit-flipping error correction algorithm which utilizes a variable bit-flipping threshold to determine whether to flip a bit in an error correction codeword. Other embodiments are also disclosed and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.